1. Field of the Invention
This invention relates to antifuses and, more specifically, to a method of fabricating an antifuse for use as part of an integrated circuit.
2. Brief Description of the Prior Art
Scaling of metal-to-metal antifuses can cause increased capacitance between adjacent metal layers along with high aspect ratio in the case of via antifuses. The increased capacitance decreases the operating speed of the circuit and the high aspect ratio decreases the yield and reliability of the antifuse.
Prior art solutions to the problem have been to directly integrate the antifuse on the bottom interconnect metal without an antifuse base. As a result, in order to maintain a sufficient separation between interconnect levels for minimal capacitance and adequate breakdown voltage, a high aspect ratio antifuse must be used having a depth equal to the thickness of the intermetal dielectric (IMD). A high aspect ratio antifuse causes severe corner cusping and nonuniformity of the amorphous silicon and results in nonuniform breakdown voltage of the antifuse. Formation of a non-self-aligned base for the antifuse increases the width of the host metal or suffers from yield loss due to tighter registration requirements.
In view of the above, in the fabrication of integrated circuits having an antifuse, it has been found desirable to provide a base for the antifuse due to unwanted capacitance that can be generated if the antifuse rests on the metal therebelow. Preferably, the antifuse is spaced sufficiently from the metal therebelow to provide low capacitance. A problem with provision of a large space between the antifuse and the metal therebelow has been the inability to provide a self-aligning structure. Accordingly, there is a penalty incurred in the form of a second alignment step.